13.Computer-Aided Design of Integrated Circuits by John G. Webster (Editor)

By John G. Webster (Editor)

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By John G. Webster (Editor)

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The time reduction is achieved by reducing the number of candidates to examine by analysis at the logic level. We shall first review diagnosis techniques based on their classification of usage of precomputed information (as opposed to run-time analysis) in the diagnosis process. The techniques are broadly grouped under static (cause–effect), dynamic (effect–cause), and integrated techniques. Then, we briefly review work on important tools required for diagnosis, diagnostic fault simulation, and diagnostic test generation.

One of the most important is the fact that sizes of BDDs are very sensitive to ordering of variables. Figure 6 shows an ex- x1 Removal of redundant nodes x2 x3 0 1 Figure 4. BDD is a canonical representation for logic functions. 224 DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING x1 x2 x3 x4 x5 x6 1 Worst 0 Best 1 3 0 1 3 1 0 0 5 5 2 0 0 1 0 5 1 0 3 0 4 4 5 Figure 6. Ordering of variables is important for BDD. 0 1 1 2 0 2 0 1 1 1 0 1 1 6 1 0 2 0 1 4 6 0 0 0 1 5 1 2 0 1 1 1 0 1 0 treme case.

This is also called a computation tree, because it represents all possible computations that can be done by the state-transition graph on the left side. Thus the goal of sequential verification is to ensure that the values of the outputs are equal to the specified values at each node of the computation tree. This can be checked by traversing the state-transition graph features one by one until a state that has been already traversed is reached. This is basically a depth-first search on computation trees.

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