By Mikko E. Waltari
For 4 many years the evolution of built-in circuits has Moore’s legislation, in response to which the variety of transistors in keeping with sq. millimeter of silicon doubles each 18 months. while transistors became swifter, making attainable ever-increasing clock charges in electronic circuits. This pattern turns out set to proceed for no less than one other decade with no slowing down. hence, within the close to destiny the processing energy of electronic circuits will proceed to extend at an accelerating speed. For analog circuits the evolution of expertise isn't as invaluable. hence, there's a development to maneuver sign processing capabilities from the analog area to the electronic one, which, in addition to bearing in mind a better point of accuracy, offers mark downs in energy intake and silicon quarter, raises robustness, hurries up the layout approach, brings flexibility and programmability, and raises the probabilities for layout reuse. in lots of functions the enter and output indications of the procedure are inherently analog, fighting all-digital realizations; at the least a conversion among analog and electronic is required on the - terfaces. as a rule, relocating the analog-digital boundary toward the skin global raises the bit expense throughout it. In telecommunications platforms the fashion to spice up bit charges is predicated on - ploying widerbandwidths and a better signal-to-noise ratio. even as radio architectures in lots of functions are evolving towards software-defined radio, one of many major features of that's the transferring of the anal- electronic boundary toward the antenna.
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Additional info for Circuit Techniques for Low-Voltage and High-Speed A/D Converters
The analysis, however, was made without going to the circuit level. To summarize, it is advantageous to use high stage resolution when the sampling capacitor is large, clearly dominating the opamp load . This is the situation in the front stages of a high resolution ADC [76, 77, 73]. 5 bits/stage architecture does not permit extensive scaling, a higher speed can be achieved with 2-bit or 3-bit stages. 7 Calibration RSD logic takes care of comparator errors, but errors in the stage gain G and the reference levels produced by the sub-DACs remain in the output code.
The droop in the differential output signal is considerably smaller than in the case of single output, since it is mostly common mode. In hold mode the signal at the output of the input buffer couples to the hold capacitor through the parasitic base-emitter capacitor of Q5. The feedthrough is minimized by connecting a feed-forward capacitor C1 from the other output of S/H Circuit Architectures 59 the input buffer to the hold node. This capacitor is implemented by employing the base-emitter junction capacitance of a BJT.
Sampling transforms a continuous time signal into a corresponding discrete time signal, while quantization converts continuous amplitude distribution into a set of discrete levels, which can be expressed with digital code words. 1 shows the principle of A/D conversion. Some A/D converter (ADC) architectures, the flash for instance, can perform sampling and quantization simultaneously, and in some ADCs, which are targeted for DC signals, no sampling is needed at all. In high performance ADCs, however, sampling and quantization are usually separated to make it possible to optimize the circuitry for both tasks without compromises.